CST334.4 Module Four

 

CST334.4 Module Four

What I learned this week:

This week we continued on Virtualizing Memory, while previous chapters had covered Segmentation as a means to virtualize our address space, it also comes with the trade-off of external fragmentation. Another method towards virtualization is paging, where a page is a fixed-size unit, allocated for a process virtual address space, and is directly associated to the physical address via page frames. Address translation is necessary for paging to happen, and requires the VPN to be translated to PFN, with which it can take the offset of its virtual address and add it to the PFN in order to find the physical address. Athough this comes with a trade-off as going to memory for translation is slow.

Thus we looked to further improve upon our idea of paging with  a sort of cache embedded in the memory management unit known as TLB or translation look-aside buffer. It's goal is to act as an address-translation cache. Dependent if the request to TLB is a hit or a miss indicates the approach we take. Assuming a hit(best case scenario) means the virtual address can be translated as it's already in the cache. If it happens to be a miss, hardware access is necessary to pull up the page table and find the translation.